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Synergistic FPGA – PS3 SPU Core

Jun 2026 – present · Runs compiled PS3 SPU programs on a Zynq-7020 at 100 MHz

A from-scratch implementation of the PlayStation 3's Cell SPU in SystemVerilog: an in-order, dual-issue, 128-bit SIMD core with 16 execution units, a 256 KB local store and an AXI4 DMA engine, running real compiled SPU programs on a PYNQ-Z2 board.

Tools: SystemVerilog · Vivado · Verilator · cocotb · C++ · AXI4 · Zynq-7020

More info

What it is

The Cell Broadband Engine in the PlayStation 3 has eight Synergistic Processing Units (SPUs): small, very wide SIMD cores with their own 256 KB local memory and no cache. This project implements one of them in RTL and runs it on an AMD Zynq-7020 FPGA.

Architecture

In-order, dual-issue 128-bit SIMD pipeline with 16 execution units split across two pipes (even and odd), the same arrangement the real hardware uses.
Scoreboarded hazard tracking, speculative issue past branches, and out-of-order completion.
6-read / 2-write LUTRAM register file for the 128 x 128-bit SPU register set.
256 KB dual-port BRAM local store.
AXI4 DMA engine for moving data between the local store and system memory.

Results

Timing closed in Vivado at 100 MHz on the Zynq-7020 (PYNQ-Z2), using 51% of LUTs and 47% of BRAM.
A bit-exact C++ reference model and cocotb testbenches cover every RTL block.
300,000 random programs plus compiled C kernels pass in Verilator with zero mismatches against the model.
4,000+ programs match the reference model when run on the actual hardware.

Why

I had already translated the SPU instruction set in software for ps3recomp. Building the core in hardware was the natural next step and a good way to learn what the instruction set actually costs in silicon.

The repository is not public yet. Ask me and I will walk you through the code.

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